Schottky contact type field effect transistors (MESFETs) comprising a compound semiconductor, basically GaAs, have been widely utilized in various high frequency communication systems or the like because the MESFETs exhibit good characteristics in a microwave band or in a millimeter wave band. Especially, high power transistors employed in these systems require high performance. While output power, amplification factor, power efficiency and the like are generally raised as the characteristics required for high power transistors, it is required to pay attention even to the response characteristic for very short times, i.e., nanosecond to millisecond, according to uses. Generally, a high power GaAs MESFET has a recessed gate structure in which a gate electrode is disposed in a groove, i.e., a recess of a semiconductor layer.
FIG. 9(f) shows a schematic cross-section of a prior art FET with a double recessed structure, disclosed in the GaAs IC Symposium Technical Digest, pp.263-266, 1994 (hereinafter referred to as literature (1)). In the figure, reference numeral 1 designates a semi-insulating GaAs substrate. A channel layer 2 is disposed on the substrate 1, and a source electrode 3, a drain electrode 4 and a gate electrode 7 are respectively disposed on the channel layer 2.
This FET is obtained by etching a portion of the channel layer 2 comprising GaAs with conventional chemical etching to form a groove, i.e., a recess 6, and forming the gate electrode 7 in the recess 6.
As one of transistor characteristics for limiting output power that is important for a high power transistor, the breakdown voltage between the gate electrode and the drain electrode (hereinafter referred to as gate breakdown voltage) is raised. The gate breakdown voltage largely depends on the distance between the gate electrode and the drain electrode. Generally, the longer this distance is, the more the gate breakdown voltage is improved.
In the FET having the recess structure shown in FIG. 9(f), since the resistance of the channel layer portion thinned by the depth of the recess 6 increases, the gate breakdown voltage depends on the channel layer portion. That is, the gate breakdown voltage is improved as the distance between the gate electrode 7 and the edge of the recess 6 becomes larger. If this distance is large, however, the distance between the gate electrode 7 and the source electrode 3 is lengthened, which causes an increase in source parasitic resistance. Therefore, the distance between the gate electrode 7 and the edge of the recess 6 should be set to the most suitable value, considering the gate breakdown voltage and the source parasitic resistance.
In addition, in the FET with the recess structure described above, when a bias voltage is applied to an input electrode, the current is delayed, i.e., output current lag occurs. Especially, it is called gate-lag when the input electrode is a gate electrode. As described in the literature (1), a double recessed structure is suitable for exceedingly improving the gate-lag with a reduction in gate breakdown voltage held to a minimum, and the double recessed gate FET is especially available.
A description is given of a method of fabricating the double recessed gate FET described in the literature (1).
FIGS. 9(a)-9(f) are cross-sectional views illustrating process steps in the fabricating method.
Initially, the conductive GaAs channel layer 2 is formed on the semi-insulating GaAs substrate 1, and the source electrode 3 and the drain electrode 4 are formed on portions of the channel layer 2 by photolithography. Then, a resist pattern 5 for forming the gate electrode 7 is formed over the portions of the channel layer 2 where the source and drain electrodes 3 and 4 are formed (FIG. 9(a)). It is required that the resist pattern 5 forms an overhanging shape as shown in FIG. 9(a), from restrictions in the following processes and, for example, an image reversal resist is used as the resist. In a high power FET, although a channel layer is often epitaxially grown by molecular beam epitaxy (MBE) or the like, it may be formed by ion implantation. In this case, the channel layer 2 is epitaxially grown and has a thickness of about 0.4 .mu.m.
Thereafter, as shown in FIG. 9(b), using the resist pattern 5 as a mask, a portion of the GaAs channel layer 2 is wet-etched with an etchant comprising, for example, a mixture of ammonia and hydrogen peroxide, to form an upper recess 6b. The depth of the recess 6b is about 0.1 .mu.m.
In the step of FIG. 9(c), a groove opposite to the resist opening and having almost the same width as the resist opening width is formed by dry etching which has a strong anisotropy, for example, reactive ion etching (RIE) using Cl.sub.2 gas or the like, thereby forming the recess 6 comprising the groove and the upper recess 6b. The depth of the groove is about 0.1 .mu.m.
Further, wet etching is performed with the same etchant as the first etchant comprising, for example, a mixture of ammonia and hydrogen peroxide, whereby the recess 6 extends in a width direction and in a depth direction as shown in FIG. 9(d). When this etching depth is about 0.1 .mu.m, the thickness of the GaAs channel layer 2 just beneath the gate electrode 7 to be formed in the following process becomes 0.1 .mu.m.
Subsequently, as shown in FIG. 9(e), a metal film, for example, a film comprising Ti and Au that are laminated, is deposited on the entire surface by an anisotropic technique, such as vacuum evaporation. At this time, the metal film 8 is formed on the resist pattern 5 as well. This metal film 8 is removed when the resist pattern 5 is removed with a solvent which can dissolve the resist pattern 5, such as an organic solvent. This is generally called lift-off. Especially, it is often employed for GaAs devices. Thereby, the gate electrode 7 is formed in the recess 6, completing the FET shown in FIG. 9(f).
In the FET with the double recessed structure that is formed as described above, the thickness of the channel layer 2 just beneath the lower recess close to the gate electrode 7 is about 0.1 .mu.m, i.e., smaller than the case of a single recessed structure. Therefore, it is hard for gate-lag to occur and the parasitic resistance becomes small. Further, since the upper recess 6b is spaced apart from the gate electrode 7, a high gate breakdown voltage is produced, like the single recessed structure, resulting in an FET having good characteristics for high power.
In the fabricating method described in the literature (1), however, since it is required to perform three etching processes (shown in FIGS. 9(b)-9(d)), so the fabrication process becomes a longer one. In addition, since the dry etching process (shown in FIG. 9(c)) generally requires high skill, reproducibility and controllability of the recess shape and the like are likely to be deteriorated.
As an FET fabricating method which can solve such problems, Japanese Published Patent Application No. Sho. 64-7664 discloses a method of fabricating an FET with a double recessed gate structure utilizing a phenomenon that etching of a layer damaged by ion implantation should be accelerated.
FIGS. 10(a)-10(d) are cross-sectional views illustrating process steps in a method of fabricating an FET with a double recessed gate structure utilizing an accelerated etching phenomenon. In these figures, the same reference numerals as those shown in FIGS. 9(a)-9(f) designate the same or corresponding parts.
Initially, as shown in FIG. 10(a), the conductive GaAs channel layer 2 serving as a channel region is epitaxially grown on the semi-insulating GaAs substrate 1, and the source electrode 3 and the drain electrode 4 are formed on portions of the channel layer 2 by photolithography or the like. Then, the resist pattern 5 having an opening at a portion where the gate electrode 7 is to be formed is formed. The cross-section of the resist pattern 5 forms an overhanging shape shown in FIG. 10(a), because the overhanging shape is convenient for the following processes. Generally, an n type GaAs layer is used as the channel layer 2, and Si is usually introduced as the dopant impurity. The dopant concentration of the channel layer 2 is generally about 10.sup.17 cm.sup.-3. In this case, the thickness of the channel layer 2 is about 0.4 .mu.m.
Thereafter, as shown in FIG. 10(b), using the resist pattern 5 as a mask, ions 9 are implanted into a portion of the GaAs channel layer 2 to form a damaged layer 10 in the vicinity of the surface of the channel layer portion. Since the ions are stopped in the resist pattern 5, no ion implantation is performed to portions of the channel layer 2, except for the portion just beneath the opening of the resist pattern 5.
Subsequently, a portion of the GaAs channel layer 2 including the damaged layer 10 is etched with an etchant comprising, for example, a mixture of ammonia and hydrogen peroxide, to form the recess 6 with a double recessed structure shown in FIG. 10(c), because the damaged layer 10 damaged by the ion implantation has a higher etching rate than that of the other portion of the channel layer 2.
Then, by vacuum evaporation and lift-off comprising depositing a gate metal on the entire surface by conventional vacuum evaporation and lifting-off the gate metal, the gate electrode 7 is formed in the recess 6, completing an FET shown in FIG. 10(d).
In the fabricating method described above, the double recessed structure is formed with one wet etching process. Therefore, the fabrication processes is simpler than the processes shown in FIGS. 9(a)-9(f). In addition, the prior art method of fabricating a double recessed structure includes a plurality of resist formation processes and the like and is considerably difficult, as compared with a method of fabricating a single recessed structure, whereas the fabricating method shown in FIGS. 10(a)-10(d) comprises a method of fabricating a single recessed structure to which only the process for implanting the ions (shown in FIG. 10(b)) is added, and, further, controllability of the recess shape and the like in this method is improved.
In the fabricating method shown in FIGS. 10(a)-10(d), however, the wet etching is performed to the damaged layer 10 having a higher etching rate simultaneously when the channel layer 2 is wet-etched, so that the controllability of the recess shape is deteriorated and the lower recess shape becomes gentle. As a result, it is difficult to further improve the gate breakdown voltage.
IEDM Technical Digest, pp.181-184, 1995 (hereinafter referred to as literature (2)) discloses a high power GaAs MESFET with a spike-gate, that is, a spike-shaped structure in which a portion of a gate electrode projects into a semiconductor layer beneath the gate electrode.
FIG. 11 is a cross-sectional view illustrating this spike-gate FET. In the FIG., reference numeral 1 designates a semi-insulating GaAs substrate. An insulating semiconductor layer 13, a delta-doped layer 14 and an insulating semiconductor layer 15 serving as a channel layer 2 are successively disposed on the substrate 1. A source electrode 3, a drain electrode 4 and SiO.sub.2 films 40 are respectively disposed on the insulating semiconductor layer 15. A gate electrode 7 is disposed in a recess 6 having a spike groove 6a.
In this FET, the gate electrode 7 makes contact with the insulating semiconductor layer 15 undoped with a dopant impurity. The channel comprises the delta-doped layer 14 having a high dopant concentration and an extremely small thickness and is separated from the gate electrode 7 by the insulating semiconductor layer 15. By using such a structure, the current control operation of the transistor is performed at a portion at which the distance between the gate electrode 7 and the channel (delta-doped layer 14), i.e., the gate length, is the shortest, that is, at the spike-shaped portion of the gate electrode 7 projecting into the semiconductor layer 15. Accordingly, this spike-gate FET realizes an extremely short gate length. Generally, the gate resistance increases with the shortened gate length, thereby degrading high frequency characteristics of an FET. In the spike-gate FET, however, since the sectional area of the gate electrode 7 itself is the same as in the prior art structure, the increase in gate resistance which degrades high frequency characteristics does not occur.
A description is given of a method of fabricating the spike-gate FET described in the literature (2).
FIGS. 12(a)-12(i) are cross-sectional views illustrating process steps in the fabricating method. In these figures, in order to simplify the figures, a detailed layer structure of the channel layer 2 is not shown.
Initially, as shown in FIG. 12(a), the channel layer 2 is epitaxially grown on the semi-insulating GaAs substrate 1, and a narrow resist pattern 30 is formed on the channel layer 2. The width of the resist pattern 30 is about 0.15 .mu.m.
Next, as shown in FIG. 12(b), the SiO.sub.2 film 40 is deposited on the entire surface by vacuum evaporation.
As shown in FIG. 12(c), lift-off of the SiO.sub.2 film 40 is performed to form a narrow opening 30a.
As shown in FIG. 12(d), by conventional photolithography and etching of the SiO.sub.2 film 40, openings for forming the source electrode 3 and the drain electrode 4 are formed in the SiO.sub.2 film 40.
Subsequently, as shown in FIG. 12(e), the source electrode 3 and the drain electrode 4 are formed in the openings of the SiO.sub.2 film 40 by vacuum evaporation and lift-off. Then, after forming a resist pattern 70 having an opening at a portion where the gate electrode 7 is to be formed, a shallow groove 2a is formed in the channel layer 2 with a mixture of tartaric acid and hydrogen peroxide. In this case, the opening width of the resist pattern 70 determines the maximum width of the gate electrode 7.
Thereafter, as shown in FIG. 12(f), the SiO.sub.2 film 40 is selectively etched in a transverse direction with, for example, a solution of hydrofluoric acid.
Then, as shown in FIG. 12(g), the channel layer 2 is selectively etched with, for example, a mixture of tartaric acid and hydrogen peroxide, to form the recess 6 having the spike groove 6a.
In the step of FIG. 12(h), a gate metal is deposited on the entire surface by vacuum evaporation and the resist pattern 70 is removed by lift-off, thereby forming the gate electrode 7 in the recess 6, completing the spike-gate FET shown in FIG. 12(i).
In the method of fabricating the spike-gate FET described above, since it is required to perform two photolithographic processes for forming the resist patterns 30 and 70, two processes for etching the GaAs channel layer 2, a few processes for forming and etching the SiO.sub.2 film 40 and the like, the fabrication process is relatively complicated.
In addition, since it is not easy to improve controllability of the etching size in a transverse direction, i.e., side etching size, of the SiO.sub.2 film 40 (shown in FIG. 12(f)), controllability of the recess shape and the like is deteriorated.
Further, in this method, because the spike groove 6a is formed automatically in the middle of the gate electrode 7, this groove cannot be offset to the source electrode side or the drain electrode side in order to improve characteristics, so that it is difficult to realize a degree of freedom in the design of the source parasitic resistance, the gate capacitance and the like.